- HIGH SPEED fMAX = 75 MHz (TYP.) AT Vcc=5V
- LOW POWER DISSIPATION Icc=2mA(MAX.)AT TA=25°C
- HIGH NOISE IMMUNITY VNIH =VNIL =28%Vcc(MIN.)
- OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS
- SYMMETRICAL OUTPUT IMPEDANCE zIOHz =IOL = 4 mA (MIN.)
- BALANCED PROPAGATION DELAYS tPLH =tPHL
- WIDE OPERATING VOLTAGE RANGE Vcc(OPR) = 2 V TO 6 V
- PIN AND FUNCTION COMPATIBLE WITH 54/74LS73
Description
The M54/74HC73 is a high speed CMOSDUAL J-K FLIP FLOP WITH CLEAR fabricated in silicon gate C2 MOStechnology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. Depending on the logic level applied to J and K inputs, this device changes state on the negative going transition of clock input pulse (CK). The clear function is accomplished independently of the clock condition when the clear input (CLR) is taken low. All inputs are equipped with protection circuits against static discharge and transient excess voltage.
