- HIGH SPEED tPD = 18 ns (TYP.) AT Vcc=5V
- LOW POWER DISSIPATION Icc=4mA(MAX.) AT TA=25°C
- HIGH NOISE IMMUNITY VNIH =VNIL =28%Vcc(MIN.)
- OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS
- SYMMETRICAL OUTPUT IMPEDANCE |IOH|=IOL = 4 mA (MIN.)
- BALANCED PROPAGATION DELAYS tPLH =tPHL
- WIDE OPERATING VOLTAGE RANGE VCC(OPR) = 2 V TO 6 V
- PIN AND FUNCTION COMPATIBLE WITH 4514B/4515B
Description
The 74HC4514 and the 74HC4515 are high speed CMOS 4-LINE TO 16-LINE DECODERS WITH LATCHED INPUTS fabricated in silicon gate C2 MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low power consumption. A binary code stored in the four input latches (A to D) provides a high level (HC4514) or a low level (HC4515) at the selected one of sixteen outputs excluding the other fifteen outputs, when the inhibit input (INHIBIT) is held low. When the inhibit input is held high, all outputs are kept low level (HC4514) or high level (HC4515), while the latch function is available. The data applied to the data inputs are transfered to the Q outputs of latches when the strobe input is held high. When the strobe input is taken low, the information data applied to the data input at a time is retained at the output of the latches. All in-puts are equipped with protection circuits against static discharge and transient excess voltage.
